InstructionInfoFactory¶
- class iced_x86.InstructionInfoFactory¶
Returns used registers and memory locations
Examples:
from iced_x86 import * # add [rdi+r12*8-5AA5EDCCh],esi data = b"\x42\x01\xB4\xE7\x34\x12\x5A\xA5" decoder = Decoder(64, data) def create_enum_dict(module): return {module.__dict__[key]:key for key in module.__dict__ if isinstance(module.__dict__[key], int)} reg_to_str = create_enum_dict(Register) op_access_to_str = create_enum_dict(OpAccess) memsz_to_str = create_enum_dict(MemorySize) info_factory = InstructionInfoFactory() for instr in decoder: print(f"Instruction: {instr}") info = info_factory.info(instr) for mem_info in info.used_memory(): # Register and OpAccess enum values print(f"Used memory:") print(f" seg: {reg_to_str[mem_info.segment]}") print(f" base: {reg_to_str[mem_info.base]}") print(f" index: {reg_to_str[mem_info.index]}") print(f" scale: {mem_info.scale}") print(f" displacement: 0x{mem_info.displacement:X}") print(f" MemorySize enum: {memsz_to_str[mem_info.memory_size]}") print(f" OpAccess enum: {op_access_to_str[mem_info.access]}") for reg_info in info.used_registers(): print(f"Used register: reg={reg_to_str[reg_info.register]} access={op_access_to_str[reg_info.access]}")
Output:
Instruction: add [rdi+r12*8-5AA5EDCCh],esi Used memory: seg: DS base: RDI index: R12 scale: 8 displacement: 0xFFFFFFFFA55A1234 MemorySize enum: UINT32 OpAccess enum: READ_WRITE Used register: reg=RDI access=READ Used register: reg=R12 access=READ Used register: reg=ESI access=READ
- info(instruction)¶
Gets all accessed registers and memory locations
- Parameters:
instruction (Instruction) – The instruction that should be analyzed
- Returns:
Accessed registers and memory locations
- Return type:
Examples:
from iced_x86 import * # add [rdi+r12*8-5AA5EDCCh],esi data = b"\x42\x01\xB4\xE7\x34\x12\x5A\xA5" decoder = Decoder(64, data) info_factory = InstructionInfoFactory() instr = decoder.decode() info = info_factory.info(instr) mem_list = info.used_memory() assert len(mem_list) == 1 mem = mem_list[0] assert mem.segment == Register.DS assert mem.base == Register.RDI assert mem.index == Register.R12 assert mem.scale == 8 assert mem.displacement == 0xFFFFFFFFA55A1234 assert mem.memory_size == MemorySize.UINT32 assert mem.access == OpAccess.READ_WRITE regs = info.used_registers() assert len(regs) == 3 assert regs[0].register == Register.RDI assert regs[0].access == OpAccess.READ assert regs[1].register == Register.R12 assert regs[1].access == OpAccess.READ assert regs[2].register == Register.ESI assert regs[2].access == OpAccess.READ