OpCodeInfo

class iced_x86.OpCodeInfo(code)

Opcode info, returned by Instruction.op_code or created by the constructor

Parameters:

code (Code) – Code value

Examples:

from iced_x86 import *

op_code = OpCodeInfo(Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256)
assert op_code.op_code_string == "EVEX.256.66.0F.W1 28 /r"
assert op_code.encoding == EncodingKind.EVEX
assert OpCodeInfo(Code.SUB_R8_RM8).op_code == 0x2A
assert OpCodeInfo(Code.CVTPI2PS_XMM_MMM64).op_code == 0x2A
address_size

(u8) (Legacy encoding) Gets the required address size (16,32,64) or 0

Type:

int

amd_decoder16

True if it’s decoded by iced’s 16-bit AMD decoder

Type:

bool

amd_decoder32

True if it’s decoded by iced’s 32-bit AMD decoder

Type:

bool

amd_decoder64

True if it’s decoded by iced’s 64-bit AMD decoder

Type:

bool

amd_lock_reg_bit

True if the LOCK prefix can be used as an extra register bit (bit 3) to access registers 8-15 without a REX prefix (eg. in 32-bit mode)

Type:

bool

amd_may_vm_exit

(AMD SVM) True if it may cause a #VMEXIT in guest mode

Type:

bool

amd_vm_exit

(AMD SVM) True if it causes a #VMEXIT in guest mode

Type:

bool

broadcast_memory_size

If it has a memory operand, gets the MemorySize (broadcast memory type)

Type:

MemorySize

can_broadcast

(EVEX) True if the instruction supports broadcasting (EVEX.b bit) (if it has a memory operand)

Type:

bool

can_suppress_all_exceptions

(EVEX/MVEX) True if the instruction supports suppress all exceptions

Type:

bool

can_use_bnd_prefix

True if the BND (F2) prefix can be used

Type:

bool

can_use_hint_taken_prefix

True if the HINT-TAKEN (3E) and HINT-NOT-TAKEN (2E) prefixes can be used

Type:

bool

can_use_lock_prefix

True if the LOCK (F0) prefix can be used

Type:

bool

can_use_notrack_prefix

True if the NOTRACK (3E) prefix can be used

Type:

bool

can_use_op_mask_register

(EVEX/MVEX) True if an opmask register can be used

Type:

bool

can_use_rep_prefix

True if the REP / REPE (F3) prefixes can be used

Type:

bool

can_use_repne_prefix

True if the REPNE (F2) prefix can be used

Type:

bool

can_use_rounding_control

(EVEX/MVEX) True if the instruction supports rounding control

Type:

bool

can_use_xacquire_prefix

True if the XACQUIRE (F2) prefix can be used

Type:

bool

can_use_xrelease_prefix

True if the XRELEASE (F3) prefix can be used

Type:

bool

can_use_zeroing_masking

(EVEX) True if the instruction supports zeroing masking (if one of the opmask registers K1-K7 is used and destination operand is not a memory operand)

Type:

bool

code

Gets the code (a Code enum value)

Examples:

from iced_x86 import *

op_code = OpCodeInfo(Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256)
assert op_code.code == Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256
Type:

Code

compatibility_mode

True if it can be executed in compatibility mode

Type:

bool

cpl0

True if it can be executed when CPL=0

Type:

bool

cpl1

True if it can be executed when CPL=1

Type:

bool

cpl2

True if it can be executed when CPL=2

Type:

bool

cpl3

True if it can be executed when CPL=3

Type:

bool

decoder_option

Gets the decoder option that’s needed to decode the instruction or DecoderOptions.NONE.

Type:

DecoderOptions

default_op_size64

True if the default operand size is 64 in 64-bit mode. A 66 prefix can switch to 16-bit operand size.

Type:

bool

encoding

Gets the encoding (an EncodingKind enum value)

Examples:

from iced_x86 import *

op_code = OpCodeInfo(Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256)
assert op_code.encoding == EncodingKind.EVEX
Type:

EncodingKind

force_op_size64

True if the operand size is always 64 in 64-bit mode. A 66 prefix is ignored.

Type:

bool

fwait

True if an FWAIT (9B) instruction is added before the instruction

Type:

bool

group_index

(i8) Group index (0-7) or -1. If it’s 0-7, it’s stored in the reg field of the modrm byte.

Type:

int

ignores_mod_bits

True if the mod bits are ignored and it’s assumed modrm[7:6] == 11b

Type:

bool

ignores_rounding_control

True if rounding control is ignored (#UD is not generated)

Type:

bool

ignores_segment

True if the instruction doesn’t read the segment register if it uses a memory operand

Type:

bool

instruction_string

Gets the instruction string, eg. VPBROADCASTB xmm1, xmm2/m8, see also OpCodeInfo.op_code_string

Examples:

from iced_x86 import *

op_code = OpCodeInfo(Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256)
assert op_code.instruction_string == "VMOVAPD ymm1 {k1}{z}, ymm2/m256"
Type:

str

intel_decoder16

True if it’s decoded by iced’s 16-bit Intel decoder

Type:

bool

intel_decoder32

True if it’s decoded by iced’s 32-bit Intel decoder

Type:

bool

intel_decoder64

True if it’s decoded by iced’s 64-bit Intel decoder

Type:

bool

intel_force_op_size64

True if the Intel decoder forces 64-bit operand size. A 66 prefix is ignored.

Type:

bool

intel_may_vm_exit

(Intel VMX) True if it may cause a VM exit in VMX non-root operation

Type:

bool

intel_smm_vm_exit

(Intel VMX) True if it causes an SMM VM exit in VMX root operation (if dual-monitor treatment is activated)

Type:

bool

intel_vm_exit

(Intel VMX) True if it causes a VM exit in VMX non-root operation

Type:

bool

is_available_in_mode(bitness)

Checks if the instruction is available in 16-bit mode, 32-bit mode or 64-bit mode

Parameters:

bitness (int) – 16, 32 or 64

Returns:

True if it’s available in the mode

Return type:

bool

is_cet_tracked

True if it’s a tracked JMP/CALL indirect instruction (CET)

Type:

bool

is_fpu_no_wait

True if it’s a no-wait FPU instruction, eg. FNINIT

Type:

bool

is_group

True if it’s part of a group

Type:

bool

is_input_output

True if the instruction accesses the I/O address space (eg. IN, OUT, INS, OUTS)

Type:

bool

is_instruction

True if it’s an instruction, False if it’s eg. Code.INVALID, db, dw, dd, dq, zero_bytes

Examples:

from iced_x86 import *

assert OpCodeInfo(Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256).is_instruction
assert not OpCodeInfo(Code.INVALID).is_instruction
assert not OpCodeInfo(Code.DECLAREBYTE).is_instruction
Type:

bool

is_lig

(VEX/XOP/EVEX) True if the L / L'L fields are ignored.

EVEX: if reg-only ops and {er} (EVEX.b is set), L'L is the rounding control and not ignored.

Type:

bool

is_non_temporal

True if it’s a non-temporal hint memory access (eg. MOVNTDQ)

Type:

bool

is_nop

True if it’s one of the many nop instructions (does not include FPU nop instructions, eg. FNOP)

Type:

bool

is_op_mask_read_write

True if the opmask register is read and written (instead of just read). This also implies that it can’t be K0.

Type:

bool

is_privileged

True if it’s a privileged instruction (all CPL=0 instructions (except VMCALL) and IOPL instructions IN, INS, OUT, OUTS, CLI, STI)

Type:

bool

is_reserved_nop

True if it’s one of the many reserved nop instructions (eg. 0F0D, 0F18-0F1F)

Type:

bool

is_rm_group

True if it’s part of a modrm.rm group

Type:

bool

is_save_restore

True if it reads/writes too many registers

Type:

bool

is_serializing_amd

True if it’s a serializing instruction (AMD CPUs)

Type:

bool

is_serializing_intel

True if it’s a serializing instruction (Intel CPUs)

Type:

bool

is_stack_instruction

True if it’s an instruction that implicitly uses the stack register, eg. CALL, POP, etc

Type:

bool

is_wig

(VEX/XOP/EVEX/MVEX) True if the W field is ignored in 16/32/64-bit modes

Type:

bool

is_wig32

(VEX/XOP/EVEX/MVEX) True if the W field is ignored in 16/32-bit modes (but not 64-bit mode)

Type:

bool

l

(u8) (VEX/XOP/EVEX) L / L'L value or default value if OpCodeInfo.is_lig is True

Type:

int

long_mode

True if it can be executed in 64-bit mode

Type:

bool

mandatory_prefix

Gets the mandatory prefix (a MandatoryPrefix enum value)

Type:

MandatoryPrefix

may_require_cpl0

True if the instruction requires either CPL=0 or CPL<=3 depending on some CPU option (eg. CR4.TSD, CR4.PCE, CR4.UMIP)

Type:

bool

memory_size

If it has a memory operand, gets the MemorySize (non-broadcast memory type)

Type:

MemorySize

mnemonic

Gets the mnemonic (a Mnemonic enum value)

Examples:

from iced_x86 import *

op_code = OpCodeInfo(Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256)
assert op_code.mnemonic == Mnemonic.VMOVAPD
Type:

Mnemonic

mode16

True if it’s an instruction available in 16-bit mode

Type:

bool

mode32

True if it’s an instruction available in 32-bit mode

Type:

bool

mode64

True if it’s an instruction available in 64-bit mode

Type:

bool

must_be_cpl0

True if it can only be executed when CPL=0

Type:

bool

mvex_can_use_eviction_hint

(MVEX) True if the instruction supports eviction hint (if it has a memory operand)

Type:

bool

mvex_can_use_imm_rounding_control

(MVEX) True if the instruction’s rounding control bits are stored in imm8[1:0]

Type:

bool

mvex_conversion_func

(MVEX) Gets the conversion function, eg. Sf32 (an MvexConvFn enum value)

Type:

MvexConvFn

mvex_eh_bit

(MVEX) Gets the EH bit that’s required to encode this instruction (an MvexEHBit enum value)

Type:

MvexEHBit

mvex_ignores_op_mask_register

(MVEX) True if the instruction ignores op mask registers (eg. {k1})

Type:

bool

mvex_no_sae_rc

(MVEX) True if the instruction must have MVEX.SSS=000 if MVEX.EH=1

Type:

bool

mvex_tuple_type_lut_kind

(MVEX) Gets the tuple type / conv lut kind (an MvexTupleTypeLutKind enum value)

Type:

MvexTupleTypeLutKind

mvex_valid_conversion_funcs_mask

(u8) (MVEX) Gets flags indicating which conversion functions are valid (bit 0 == func 0)

Type:

int

mvex_valid_swizzle_funcs_mask

(u8) (MVEX) Gets flags indicating which swizzle functions are valid (bit 0 == func 0)

Type:

int

nfx

True if the F2/F3 prefixes aren’t allowed

Type:

bool

no66

True if the 66 prefix is not allowed (it will #UD)

Type:

bool

op0_kind

Gets operand #0’s opkind (an OpCodeOperandKind enum value)

Type:

OpCodeOperandKind

op1_kind

Gets operand #1’s opkind (an OpCodeOperandKind enum value)

Type:

OpCodeOperandKind

op2_kind

Gets operand #2’s opkind (an OpCodeOperandKind enum value)

Type:

OpCodeOperandKind

op3_kind

Gets operand #3’s opkind (an OpCodeOperandKind enum value)

Type:

OpCodeOperandKind

op4_kind

Gets operand #4’s opkind (an OpCodeOperandKind enum value)

Type:

OpCodeOperandKind

op_code

(u32) Gets the opcode byte(s). The low byte(s) of this value is the opcode. The length is in OpCodeInfo.op_code_len. It doesn’t include the table value, see OpCodeInfo.table.

Examples:

from iced_x86 import *

assert OpCodeInfo(Code.FFREEP_STI).op_code == 0xDFC0
assert OpCodeInfo(Code.VMRUNW).op_code == 0x01D8
assert OpCodeInfo(Code.SUB_R8_RM8).op_code == 0x2A
assert OpCodeInfo(Code.CVTPI2PS_XMM_MMM64).op_code == 0x2A
Type:

int

op_code_len

(u8) Gets the length of the opcode bytes (OpCodeInfo.op_code). The low bytes is the opcode value.

Examples:

from iced_x86 import *

assert OpCodeInfo(Code.FFREEP_STI).op_code_len == 2
assert OpCodeInfo(Code.VMRUNW).op_code_len == 2
assert OpCodeInfo(Code.SUB_R8_RM8).op_code_len == 1
assert OpCodeInfo(Code.CVTPI2PS_XMM_MMM64).op_code_len == 1
Type:

int

op_code_string

Gets the opcode string, eg. VEX.128.66.0F38.W0 78 /r, see also OpCodeInfo.instruction_string

Examples:

from iced_x86 import *

op_code = OpCodeInfo(Code.EVEX_VMOVAPD_YMM_K1Z_YMMM256)
assert op_code.op_code_string == "EVEX.256.66.0F.W1 28 /r"
Type:

str

op_count

(u8) Gets the number of operands

Type:

int

op_kind(operand)

Gets an operand’s opkind (an OpCodeOperandKind enum value)

Parameters:

operand (int) – Operand number, 0-4

Returns:

Operand kind

Return type:

OpCodeOperandKind

Raises:

ValueError – If operand is invalid

op_kinds()

Gets all operand kinds (a list of OpCodeOperandKind enum values)

Returns:

All operand kinds

Return type:

List[OpCodeOperandKind]

operand_size

(u8) (Legacy encoding) Gets the required operand size (16,32,64) or 0

Type:

int

protected_mode

True if it can be executed in protected mode

Type:

bool

real_mode

True if it can be executed in real mode

Type:

bool

require_op_mask_register

(EVEX/MVEX) True if a non-zero opmask register must be used

Type:

bool

requires_unique_dest_reg_num

True if the destination register’s reg-num must not be present in any other operand, eg. MNEMONIC XMM1,YMM1,[RAX+ZMM1*2] is invalid. Registers = XMM/YMM/ZMM/TMM.

Type:

bool

requires_unique_reg_nums

True if the index reg’s reg-num (vsib op) (if any) and register ops’ reg-nums must be unique, eg. MNEMONIC XMM1,YMM1,[RAX+ZMM1*2] is invalid. Registers = XMM/YMM/ZMM/TMM.

Type:

bool

rm_group_index

(i8) Group index (0-7) or -1. If it’s 0-7, it’s stored in the rm field of the modrm byte.

Type:

int

table

Gets the opcode table (an OpCodeTableKind enum value)

Type:

OpCodeTableKind

tdx_non_root_gen_ud

True if #UD is generated in TDX non-root operation

Type:

bool

tdx_non_root_gen_ve

True if #VE is generated in TDX non-root operation

Type:

bool

tdx_non_root_may_gen_ex

True if an exception (eg. #GP(0), #VE) may be generated in TDX non-root operation

Type:

bool

tsx_abort

True if it causes a TSX abort inside a TSX transaction

Type:

bool

tsx_impl_abort

True if it causes a TSX abort inside a TSX transaction depending on the implementation

Type:

bool

tsx_may_abort

True if it may cause a TSX abort inside a TSX transaction depending on some condition

Type:

bool

tuple_type

(EVEX/MVEX) Gets the tuple type (a TupleType enum value)

Type:

TupleType

use_in_enclave_sgx1

True if it can be used inside an enclave (SGX1)

Type:

bool

use_in_enclave_sgx2

True if it can be used inside an enclave (SGX2)

Type:

bool

use_in_seam

True if it can be used in SEAM

Type:

bool

use_in_smm

True if it can be used in SMM

Type:

bool

use_in_vmx_non_root_op

True if it can be used in VMX non-root operation

Type:

bool

use_in_vmx_root_op

True if it can be used in VMX root operation

Type:

bool

use_outside_enclave_sgx

True if it can be used outside an enclave (SGX)

Type:

bool

use_outside_seam

True if it can be used outside SEAM

Type:

bool

use_outside_smm

True if it can be used outside SMM

Type:

bool

use_outside_vmx_op

True if it can be used outside VMX operation

Type:

bool

virtual8086_mode

True if it can be executed in virtual 8086 mode

Type:

bool

w

(u8) (VEX/XOP/EVEX/MVEX) W value or default value if OpCodeInfo.is_wig or OpCodeInfo.is_wig32 is True

Type:

int