# Generated by makepkg 7.0.0
# using fakeroot version 1.37.1.2
pkgname = vtr
pkgbase = vtr
xdata = pkgtype=pkg
pkgver = 9.0.0-1
pkgdesc = Verilog to Routing -- Open Source CAD Flow for FPGA Research
url = https://verilogtorouting.org
builddate = 1766429942
packager = Felix Yan <felixonmars@archlinux.org>
size = 22667235
arch = riscv64
license = MIT
depend = ctags
depend = tbb
makedepend = cmake
makedepend = wget
